In an industry where more and more functions are integrated at each new generation of systems while process nodes are constantly shrinking, SoC and Platform architects must take into account power issues very early in their design flow and explore the largest possible space of use scenarios.
So the question is how to explore the best strategies for low power design with the increasing complexity of systems and scenarios? Moreover, when both power and temperature become key factors in your design, a separate approach is risky in terms of reliability.
At the architectural level for IP blocks, SoC, SiP or platforms, our solution enables architects to make the right architectural choices to optimize power consumption and reduce risks related to power issues earlier.
Thanks to early decisions and predictions in the design flow, power saving can reach 40-70% at the Electronic System Level versus 10-25% later at physical design. ESL is where you have the biggest impact on power consumption in your architecture. Power-saving opportunities at the RTL and gate-level are limited and have a much smaller impact on the total power consumption.
We provide an ESL solution to model, simulate and explore power and thermal aspects of your architecture. The solution allows to capture use cases and explore all possible power management strategies, including multiple voltage domains modelling, DPM (dynamic power management), DVFS (dynamic voltage-frequency scaling), clock gating, retention mode, and identify the best configuration for the application use cases. Use of high level power reduction techniques such as multi-level clock gating can be modelled at ESL. What you get is a comprehensive power planning for implementation teams – specifications, support of UPF, dynamic and static power reports, detailed scenarios.
One of the key advantages of the DOCEA Power methodology is the ability to manage power data without modifying existing design flow: the chosen modelling strategy within DOCEA's solution is to have a separate power model from the functional model. This makes both models (functional and power) easier to debug and better suited for design space exploration.
Another key advantage within our solutions is that the architectural description is separated from the application use cases. This also improves the reuse of power and thermal models and their sharing among development teams and projects to capitalize the know-how. This methodology enables system designers to make trade-offs between performance and power consumption, and measure the impact of software on power consumption. Optimal hardware/software partitioning for power can only be done at ESL. How much power can your hardware handle? How much should work should you assign to your embedded core (software) instead? DOCEA’s solution has an automated way to map power information from the gate level block representations into the transaction-level modeling (TLM) domain which maintains a high fidelity of modeling accuracy.
Cases where temperature is an issue:
Within some projects, meeting the specifications for max Temperature is an issue. Within others, physics make Power dependent on Temperature with a strong coupling: in these applications it is temperature that can make you exceed the power budget. For both cases, our solutions allow you to perform electro-thermal simulations and take into account the coupling effect.
A holistic approach for managing power and thermal issues at the architectural level
Better power and thermal predictions help to design efficient products in accordance with customers’ requirements and environmental policies. Our solutions enable designers to speed up architectures’ definitions. By exploring a larger design space both for the hardware and the software impact on power consumption and temperature, our solutions help architects reach the optimum architecture for their projects and provides implementation teams with comprehensive specifications.